Publications

A record of 13 peer-reviewed papers, 5 workshop papers, and 2 preprints. Links point to available publication records.

Peer-Reviewed Papers

Papers spanning LLM systems, low-power accelerators, and neuromorphic hardware.

Characterization of Request and Token Energy Costs for LLM Inference Workloads on GPU Platforms

P. Vellaisamy, V. Lam, S. Blanton, J.P. Shen

IEEE International Symposium on Workload Characterization (IISWC) 2026 arXiv:2608.28044

Accepted

TaxBreak: Unmasking the Hidden Costs of LLM Inference Through Overhead Decomposition

P. Vellaisamy, S. Tripathi, V. Natarajan, S.S. Thenarasu, R.D.S. Blanton, J.P. Shen

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2026 arXiv:2603.12465

Mugi: Value Level Parallelism For Efficient LLMs

D. Price, P. Vellaisamy, J.P. Shen, D. Wu

ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2026 arXiv:2601.10823

Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks

D. Lister, P. Vellaisamy, J.P. Shen, D. Wu

IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2025 arXiv:2508.21267

Amar Mukherjee Best Paper Award

Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architectures

P. Vellaisamy, T. Labonte, S. Chakraborty, M. Turner, S. Sury, J.P. Shen

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2025 arXiv:2504.11750

Invited talk at Jülich Supercomputing Center

Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs

P. Vellaisamy, H. Nair, T. Kang, Y. Ni, H. Fan, B. Qi, J. Chen, R.D.S. Blanton, J.P. Shen

IEEE Design, Automation & Test in Europe (DATE) 2025 arXiv:2412.19002

Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference

H. Nair, P. Vellaisamy, T.H. Lin, P. Wang, R.D.S. Blanton, J.P. Shen

IEEE VLSI-SoC 2024 arXiv:2402.19376

Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators

P. Vellaisamy, H. Nair, D. Wu, R.D.S. Blanton, J.P. Shen

IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024 arXiv:2602.00838

Realtime Person Identification via Gait Analysis using IMU Sensors on Edge Devices

S. Venkatachalam, H. Nair, P. Vellaisamy, Y. Zhou, Z. Youssfi, J.P. Shen

International Conference on Neuromorphic Systems (ICONS) 2024 DOI

TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering

P. Vellaisamy, H. Nair, V. Ratnakaram, D. Gupta, J.P. Shen

IEEE Transactions on Circuits and Systems II: Express Briefs 71(5), 2024 · Presented at ISCAS 2024 arXiv:2412.17977

tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit

P. Vellaisamy, H. Nair, J. Finn, M. Trivedi, A. Chen, A. Li, T.H. Lin, P. Wang, R.D.S. Blanton, J.P. Shen

IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2023 arXiv:2412.17955

tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low-Precision Edge AI

H. Nair, P. Vellaisamy, A. Chen, J. Finn, A. Li, M. Trivedi, J.P. Shen

IEEE International Symposium on Circuits and Systems (ISCAS) 2023 arXiv:2412.17966

TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs

H. Nair, P. Vellaisamy, S. Bhasuthkar, J.P. Shen

IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2022 arXiv:2205.07410

Preprints

Manuscripts currently available in preprint form.

NeuroAI Temporal Neural Networks (NeuTNNs): Microarchitecture and Design Framework for Specialized Neuromorphic Processing Units

S. Venkatachalam, P. Vellaisamy, H. Nair, W.C. Huang, Y. Na, Y. Kang, Q. Jacobson, J.P. Shen

arXiv preprint, February 2026 arXiv:2602.01546

Preprint

A-Graph: A Unified Graph Representation for At-Will Simulation across System Stacks

D. Price, P. Vellaisamy, P. Gonzalez, G. Michelogiannakis, J.P. Shen, D. Wu

arXiv preprint, February 2026 arXiv:2602.04847

Preprint

Workshop Papers

Workshop papers that helped shape the larger research program.

Mugi: Value Level Parallelism For Nonlinear Operations in LLMs

D. Price, P. Vellaisamy, J.P. Shen, D. Wu

Workshop on Unary Computing (WUC), ASPLOS 2026

Agraph: A Unified Graph Representation for At-Will Simulation of Emerging Stacks

D. Price, P. Vellaisamy, J.P. Shen, D. Wu

Workshop on Unary Computing (WUC), ASPLOS 2026

Exploration of Unary Based GEMM Designs for Conventional AI/DL Accelerators

P. Vellaisamy, H. Nair, D. Wu, J.P. Shen

2nd Workshop on Unary Computing (WUC), ASPLOS 2024

xBrain: Brain-Like Computing for Explainable Brain-Computer Interfaces

Q. Xi, P. Vellaisamy, D. Wu

Young Architect Workshop (YArch), ASPLOS 2024 YArch 2024

Towards a Design Framework for TNN-Based Neuromorphic Sensory Processing Units

P. Vellaisamy, J.P. Shen

Young Architect Workshop (YArch), ASPLOS 2022 arXiv:2205.14248