News

Offer accepted for an AI Research Scientist Intern role at Samsung Semiconductor Inc. in San Jose, CA for Jun 2026 to Sep 2026.

Offer accepted for a Silicon Solution Engineering Intern role at NVIDIA Corporation in Santa Clara, CA for Mar 2026 to Jun 2026.

"Mugi: Value Level Parallelism for Efficient LLMs" accepted at ACM ASPLOS 2026. Joint work with D. Price, J.P. Shen, and D. Wu.

"Mugi: Value Level Parallelism For Nonlinear Operations in LLMs" and "Agraph: A Unified Graph Representation for At-Will Simulation of Emerging Stacks" accepted at Workshop on Unary Computing (WUC), ASPLOS 2026.

"NeuroAI Temporal Neural Networks (NeuTNNs): Microarchitecture and Design Framework for Specialized Neuromorphic Processing Units" posted to arXiv (arXiv:2602.01546). Proposes NeuTNNs with active dendrites; NeuTNNGen achieves 30–50% synapse count reduction.

"A-Graph: A Unified Graph Representation for At-Will Simulation across System Stacks" posted to arXiv (arXiv:2602.04847).

"TaxBreak: Unmasking the Hidden Costs of LLM Inference Through Overhead Decomposition" accepted at IEEE ISPASS 2026 after peer review. The paper is also available on arXiv (arXiv:2603.12465).

Received the Amar Mukherjee Best Paper Award at IEEE ISVLSI 2025 for "Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks."

Gave an invited talk at the Jülich Supercomputing Center, Jülich, Germany (remote) on "Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architectures."

Presented "Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architectures" at IEEE ISPASS 2025.

Presented "Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs" at IEEE DATE 2025.

"TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering" was accepted at ISCAS 2024 and invited for publication in TCAS-II: Express Briefs.

Received the 2023 Qualcomm Innovation Fellowship - North America.