News
Announcements, milestones, and publication updates from the research program.
2026
- Jul 2026 Joined NVIDIA full-time as a Silicon CoDesign EngineerAccepted and started a full-time Silicon CoDesign Engineer role at NVIDIA Corporation in Santa Clara, CA in July 2026, while continuing the PhD program at Carnegie Mellon University.
- Mar 2026 TaxBreak published at ISPASS 2026"TaxBreak: Unmasking the Hidden Costs of LLM Inference Through Overhead Decomposition" was published at IEEE ISPASS 2026 and presented on April 27, 2026. The paper is also available on arXiv (arXiv:2603.12465).
- Mar 2026 Started Silicon Solution Engineering Internship at NVIDIAStarted the Silicon Solution Engineering Intern role at NVIDIA Corporation in Santa Clara, CA for Mar 2026 to Jun 2026.
- Feb 2026 Preprint: NeuroAI Temporal Neural Networks (NeuTNNs)"NeuroAI Temporal Neural Networks (NeuTNNs): Microarchitecture and Design Framework for Specialized Neuromorphic Processing Units" posted to arXiv (arXiv:2602.01546). Proposes NeuTNNs with active dendrites; NeuTNNGen achieves 30–50% synapse count reduction.
- Feb 2026 Preprint: A-Graph — Unified Graph Representation for Cross-Stack Simulation"A-Graph: A Unified Graph Representation for At-Will Simulation across System Stacks" posted to arXiv (arXiv:2602.04847).
- Jan 2026 Paper accepted at ASPLOS 2026"Mugi: Value Level Parallelism for Efficient LLMs" accepted at ACM ASPLOS 2026. Joint work with D. Price, J.P. Shen, and D. Wu.
- Jan 2026 Two Workshop Papers accepted at ASPLOS 2026 WUC"Mugi: Value Level Parallelism For Nonlinear Operations in LLMs" and "Agraph: A Unified Graph Representation for At-Will Simulation of Emerging Stacks" accepted at Workshop on Unary Computing (WUC), ASPLOS 2026.
2025
- Jul 2025 Amar Mukherjee Best Paper Award — ISVLSI 2025Received the Amar Mukherjee Best Paper Award at IEEE ISVLSI 2025 for "Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks."
- May 2025 Invited Talk at Jülich Supercomputing CenterGave an invited talk at the Jülich Supercomputing Center, Jülich, Germany (remote) on "Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architectures."
- May 2025 Paper presented at ISPASS 2025, Ghent, BelgiumPresented "Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architectures" at IEEE ISPASS 2025.
- Apr 2025 Paper presented at DATE 2025, Lyon, FrancePresented "Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs" at IEEE DATE 2025.
2024
- 2024 TNNGen published in TCAS-II and presented at ISCAS 2024"TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering" was published in IEEE TCAS-II: Express Briefs and presented at ISCAS 2024.
2023
- Oct 2023 Qualcomm Innovation Fellowship — North AmericaReceived the 2023 Qualcomm Innovation Fellowship - North America.